In the semiconductor industry, an interconnect structure is used to provide wiring between devices on an IC chip and the overall package. See, for example, U.S. Pat. Nos. 5,071,518, 5,098,860, 5,354,712, 5,545,927, 5,891,802, 5,899,740, 5,904,565, 5,933,753, 6,181,012 and 6,465,376. In such technology, the devices such as field effect transistors (FETs) are first formed on a surface of a semiconductor substrate and then an interconnect structure is formed in the BEOL. A typical interconnect structure includes at least one dielectric material having a dielectric constant of about 4.0 or lower in which metal patterns in the form of vias and/or lines are embedded therein. The interconnect structure can be either a single damascene structure or a dual damascene structure.
FIGS. 1A-1D illustrate various prior art dual damascene structures. Each of the dual damascene structures shown comprises a first dielectric 100 that includes a metal interconnect or line 110 which extends perpendicular to the plane of the paper. A first patterned cap layer 120 is also present on a surface of the first dielectric 100. A second dielectric 130 is located atop the first dielectric 100. The second dielectric 130 has a dual damascene aperture, which includes a lower portion 148 and an upper portion 150, formed therein. The lower portion 148 is referred to in the art as a via, while the upper portion 150 is referred to in the art as a line. The dielectrics used in each of the levels are typically comprised of silicon dioxide, a thermosetting polyarylene resin, an organosilicate glass such as a carbon-doped oxide (SiCOH), or any other type of hybrid related dielectric. The via 148 makes contact with the underlying interconnect 110, while the line 150 extends over a significant distance to make contact with other elements of the IC as required by the specific design layout. In the drawings, the portion of the cap layer 120 at the bottom of the via 148 has been removed, usually by a different etching chemistry than that used to etch the second dielectric 130. A patterned hard mask 122 is located atop the second dielectric 130.
It is conventional in the prior art to deposit a liner 140 over the entire interior of the structure before metallization. Liner 140 can be a single layer such as shown in FIG. 1A and FIG. 1C, or multiple layers 140, 145, as shown in FIGS. 1B and 1D. In FIGS. 1C and 1D, the liner 140 is not located on the bottom horizontal surface of the via 148. The liner 140, 145 is comprised of a refractory metal such as, for example, Ta, Ti, and W, or a refractory metal nitride such as TaN, TiN, and WN. An optional adhesion layer, not specifically shown, can be used to enhance the bonding of the liner to the second dielectric layer 130.
A conductive material (not specifically shown) such as Al, W, Cu or alloys thereof is then deposited so as to completely fill the aperture providing conductively filled vias and conductively filled lines.
One major problem with the prior art interconnect structures shown in FIGS. 1A-1D is that it is difficult to obtain a good mechanical contact at normal chip operation temperatures. Additionally, the prior art interconnect structures oftentimes exhibit an open circuit or high resistance joint during reliability testing. Hence, there is a need for providing a new and improved interconnect structure that avoids the problems mentioned above. That is, an interconnect structure is needed that has and maintains good mechanical contact during normal chip operations and does not fail during various reliability tests such as thermal cycling and high temperature baking.